Logic circuit capable of preventing latch-up

ABSTRACT

There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. patent application Ser. No. 17/206,862 filed on Mar. 19, 2021, the full disclosure of which is incorporated herein by reference.

To the extent any amendments, characterizations, or other assertions previously made (in this or in any related patent applications or patents, including any parent, sibling, or child) with respect to any art, prior or otherwise, could be construed as a disclaimer of any subject matter supported by the present disclosure of this application, Applicant hereby rescinds and retracts such disclaimer. Applicant also respectfully submits that any prior art previously considered in any related patent applications or patents, including any parent, sibling, or child, may need to be re-visited.

BACKGROUND 1. Field of the Disclosure

This disclosure generally relates to a logic circuit and, more particularly, to a standard logic cell that prevents the latch-up of a parasitic silicon control rectifier (SCR) between the source of a PMOS transistor and the source of an NMOS transistor.

2. Description of the Related Art

In the CMOS integrated circuit, the parasitic bipolar transistor structure is created corresponding to forming of the MOS transistor. In a PMOS transistor of the CMOS transistor, a P+ active region used as a source of the PMOS transistor longitudinally forms a parasitic PNP bipolar transistor with an n-well region and a p-well region. In an NMOS transistor of the CMOS transistor, an N+ active region used as a source of the NMOS transistor transversally forms a parasitic NPN bipolar transistor with the p-well region and the n-well region.

The parasitic PNP bipolar transistor and the parasitic NPN bipolar transistor together form a parasitic PNPN structure. When the PNPN structure is conducted, the latch-up is formed.

The latch-up means that the circuit formed by the parasitic bipolar transistors in the CMOS integrated circuit is triggered in a specific condition to form a low resistance path through which a large current passes. With the existence of positive feedback loop, the latch-up occurs to cause the CMOS integrated circuit unable to work normally or even cause the chip to be damaged. It is known that the abnormal large current can be detected using an additional circuit and normal work of the circuit can be recovered by resetting the system. However, resetting the system during operation is not a realistic option.

Accordingly, the present disclosure further provides a logic circuit that can prevent the latch-up without altering the routing of digital circuit or changing the circuit structure.

SUMMARY

The present disclosure provides a logic circuit that increases the holding voltage by additionally doping a P+ active region and an N+ active region so as to prevent the latch-up of a silicon control rectifier.

The present disclosure provides a logic circuit including an n-well region, a PMOS transistor, an N+ active region, an N+ guard ring, a p-well region, an NMOS transistor, a P+ active region and an additional n-well region. The PMOS transistor is arranged in the n-well region. The N+ active region is arranged in the n-well region adjacent to a source of the PMOS transistor. The N+ guard ring is arranged in the n-well region and physically separated from the N+ active region. The NMOS transistor is arranged in the p-well region. The P+ active region is arranged in the p-well region adjacent to a source of the NMOS transistor. The additional n-well region is arranged between the PMOS transistor and the NMOS transistor, and physically separated from the N+ guard ring.

The present disclosure further provides a logic circuit including a PMOS transistor, an NMOS transistor, a third contact and an additional n-well region. A gate of the PMOS transistor is electrically connected to a gate of the NMOS transistor via a poly routing extending along a first direction. A first contact of the PMOS transistor covers on a P+ active region, which is configured as a source of the PMOS transistor, and an additional N+ active region adjacent to each other in the first direction in an n-well region. A second contact of the NMOS transistor covers on an N+ active region, which is configured as a source of the NMOS transistor, and an additional P+ active region adjacent to each other in the first direction in a p-well region. The third contact covers on an N+ guard ring, which is physically separated from the additional N+ active region, in the n-well region. The additional n-well region is arranged between the PMOS transistor and the NMOS transistor, and physically separated from the N+ guard ring.

The present disclosure provides a logic circuit including an n-well region, a PMOS transistor, an N+ active region, a p-well region, an NMOS transistor, a P+ active region and an additional n-well region. The PMOS transistor is arranged in the n-well region. The N+ active region is arranged in the n-well region adjacent to a source of the PMOS transistor. The NMOS transistor is arranged in the p-well region and adjacent to the PMOS transistor in a first direction. The P+ active region is arranged in the p-well region adjacent to a source of the NMOS transistor. The additional n-well region is arranged between the PMOS transistor and the NMOS transistor. The N+ active region and the P+ active region are opposite to each other in the first direction across the additional n-well region.

The latch-up of a parasitic SCR is known to the art, and thus details thereof are not described herein. The present disclosure is to provide a circuit structure capable of preventing the occurrence of latch-up.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, advantages, and novel features of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 is an upper view of a logic circuit according to one embodiment of the present disclosure.

FIG. 2 is a cross sectional view along line A-A′ in the logic circuit of FIG. 1 .

FIG. 3A is a schematic diagram of a logic circuit of the present disclosure interfered by electric holes.

FIG. 3B is a schematic diagram of a logic circuit of the present disclosure interfered by electrons.

FIG. 4 is a circuit diagram of a parasitic silicon control rectifier of a logic circuit according to one embodiment of the present disclosure.

FIG. 5 is a transmission line pulse I-V curve of a parasitic silicon control rectifier of a logic circuit according to one embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENT

It should be noted that, wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The structure of the present disclosure is adapted to an internal logic circuit of an integrated circuit package, e.g., a CMOS integrated circuit, but not limited thereto. In the logic circuit that adopts a poly routing to connect gates of PMOS and NMOS transistors, because there is no guard ring between the PMOS transistor and the NMOS transistor, the parasitic silicon control rectifier (SCR) thereof is easily triggered by the external interference (e.g., radiation) to cause the latch-up. Therefore, the present disclosure increases an occurrence condition of the latch-up by additionally doping a P+ active region and an N+ active region.

Please referring to FIGS. 1 and 2 , FIG. 1 is an upper view of a logic circuit 100 according to one embodiment of the present disclosure, and FIG. 2 is a cross sectional view along line A-A′ in the logic circuit 100 of FIG. 1 . The logic circuit 100 includes a PMOS transistor and an NMOS transistor arranged along a first direction (e.g., Y-direction in FIG. 1 ).

The PMOS transistor includes a P+ active region 121 used as a source, a P+ active region 151 used as a drain, a gate 14 and an N+ guard ring 131 doped in the n-well region NW. In this embodiment, the N+ guard ring 131 is arranged only at a side far from the NMOS transistor without extending between the PMOS transistor and the NMOS transistor, as shown in FIG. 1 .

The NMOS transistor includes an N+ active region 122 used as a source, an N+ active region 152 uses as a drain, a gate 14 and a P+ guard ring 132 doped in the p-well region PW. In this embodiment, the P+ guard ring 132 is arranged only at a side far from the PMOS transistor without extending between the PMOS transistor and the NMOS transistor, as shown in FIG. 1 .

Because there is no guard ring between the PMOS transistor and the NMOS transistor, the gate 14 of the PMOS transistor and the gate 14 of the NMOS transistor are electrically connected via a poly routing in the first direction Y. It is appreciated that the pattern of the poly routing is not limited to those (e.g., regions filled with crossed lines in FIG. 1 ) shown in FIG. 1 as long as the gates 14 of the PMOS and NMOS transistors are connected thereby.

The PMOS transistor further includes a first contact 111C covering on and electrically in contact with the P+ active region 121, and a third contact 113C covering on and electrically in contact with the N+ guard ring 131, wherein the third contact 113C and the first contact 111C are physically separated from each other on a surface of the PMOS transistor. In operation, the third contact 113C and the first contact 111C are together connected to a voltage source V_(DD), as shown in FIG. 3B.

The NMOS transistor further includes a second contact 112C covering on and electrically in connect with the N+ active region 122, and a fourth contact 114C covering on and electrically in contact with the P+ guard ring 132, wherein the fourth contact 114C and the second contact 112C are physically separated from each other on a surface of the NMOS transistor. In operation, the second contact 112C and the fourth contact 114C are together connected to a ground voltage V_(SS), a voltage thereof being lower than the voltage source V_(DD), as shown in FIG. 3A.

The P+ active region 121 used as a source of the PMOS transistor, the n-well region NW and the p-well region PW of the PMOS transistor longitudinally form a parasitic PNP structure 101. The N+ active region 122 used as a source of the NMOS transistor, the p-well region PW and the n-well region NW of the PMOS transistor transversally form a parasitic NPN structure 103. The parasitic PNP structure 101 and the parasitic NPN structure together form a silicon control rectifier (SCR), which is known to the art and thus details thereof are not described.

When the logic circuit 100 is interfered by electric holes, a resistor R_PW of the p-well region PW has a voltage drop thereon. When the voltage drop is larger than a threshold voltage (e.g., 0.7 volt), the parasitic NPN structure 103 is conducted to operate in the amplifying state and create a positive feedback to conduct the parasitic PNP structure 101 such that the latch-up is created. In the present disclosure, to prevent the occurrence of latch-up, the NMOS transistor further includes an additional P+ active region 124 arranged in the p-well region PW, and the second contact 112C covers on and electrically contacts the N+ active region 122 and the additional P+ active region 214 which are adjacent to each other along the Y-direction.

In one aspect, the N+ active region 122 and the additional P+ active region 124 in the p-well region PW connect to each other inside the p-well region PW by silicide. More specifically, at least a part of a doping region of the N+ active region 122 overlaps a doping region of the additional P+ active region 124 inside the p-well region PW.

In another aspect, the N+ active region 122 and the additional P+ active region 124 in the p-well region PW are separated from each other inside the p-well region PW. That is, a doping region of the N+ active region 122 does not overlap a doping region of the additional P+ active region 124 inside the p-well region PW. For example, the second contact 112C has a larger area to cover both the N+ active region 122 and the additional P+ active region 124; or, a second sub-contact is respectively arranged on the N+ active region 122 and the additional P+ active region 124, and the second sub-contacts are connected via a metal line to form the second contact 112C.

As shown in FIG. 3A, when the source and the P+ guard ring 132 of the NMOS transistor are connected to the ground voltage V_(SS), by additionally arranging a P+ active region 124, a part of electric holes are absorbed by the additional P+ active region 124 rather than passing the resistor R_PW of the p-well region PW so as to reduce the voltage drop on the resistor R_PW of the p-well region PW thereby preventing the parasitic NPN structure 103 from being conducted. Furthermore, as shown in FIG. 4 , the additional P+ active region 124 forces two ends of the resistor R_PW of the p-well region PW to be connected to the ground voltage V_(SS) so as to remove the voltage drop on the resistor R_PW.

When the logic circuit 100 is interfered by electrons, a resistor R_NW of the n-well region NW has a voltage drop thereon. When the voltage drop is larger than a threshold voltage (e.g., 0.7 volt), the parasitic PNP structure 101 is conducted to operate in the amplifying state and create a positive feedback to conduct the parasitic NPN structure 103 such that the latch-up is created. In the present disclosure, to prevent the occurrence of latch-up, the PMOS transistor further includes an additional N+ active region 123 arranged in the n-well region NW, and the first contact 111C covers on and electrically contacts the P active region 121 and the additional N+ active region 123 which are adjacent to each other along the Y-direction.

In one aspect, the P+ active region 121 and the additional N+ active region 123 in the n-well region NW connect to each other inside the n-well region NW by silicide. More specifically, at least a part of a doping region of the P+ active region 121 overlaps a doping region of the additional N+ active region 123 inside the n-well region NW.

In another aspect, the P+ active region 121 and the additional N+ active region 123 in the n-well region NW are separated from each other inside the n-well region NW. That is, a doping region of the P+ active region 121 does not overlap a doping region of the additional N+ active region 123 inside the n-well region NW. For example, the first contact 111C has a larger area to cover both the P+ active region 121 and the additional N+ active region 123; or, a first sub-contact is respectively arranged on the P+ active region 121 and the additional N+ active region 123, and the first sub-contacts are connected via a metal line to form the first contact 111C.

As shown in FIG. 3B, when the source and the N+ guard ring 131 of the PMOS transistor are connected to the voltage source V_(DD), by additionally arranging an N+ active region 123, a part of electrons are absorbed by the additional N+ active region 123 rather than passing the resistor R_NW of the n-well region NW so as to reduce the voltage drop on the resistor R_NW of the n-well region NW thereby preventing the parasitic PNP structure 101 from being conducted. Furthermore, as shown in FIG. 4 , the additional N+ active region 123 forces two ends of the resistor R_NW of the n-well region NW to be connected to the voltage source V_(DD) so as to remove the voltage drop on the resistor R_NW.

As shown in FIG. 5 , the present disclosure increases the holding voltage Vhold (e.g., shown to be larger than 1.1×V_(DD)) from a latch-up zone into a latch-up free zone by doping N+ active region 123 and P+ active region 124 so as to reduce the possibility of triggering the SCR into the latch-up state.

It should be mentioned that although FIG. 1 shows that the additional P+ active regions 124 of the NMOS transistor are arranged at a side, close to the PMOS transistor, of the N+ active region 122 of the NMOS transistor, and the additional N+ active regions 123 of the PMOS transistor are arranged at a side, close to the NMOS transistor, of the P+ active region 121 of the PMOS transistor, the present disclosure is not limited thereto. It is possible to arrange the N+ active regions 123 at a transverse direction (e.g., X-direction in FIG. 1 ) adjacent to the P+ active region 121, and the P+ active regions 124 are arranged in the transverse direction X adjacent to the N+ active region 122 as long as the additional heavily doped regions are close to a space between the PMOS transistor and the NMOS transistor as much as possible.

In another aspect, in the case that the chip is interfered only by positive charges or electric holes, it is possible to add an additional P+ active region 124 in the NMOS transistor without adding the N+ active region 123 in the PMOS transistor. In an alternative aspect, in the case that the chip is interfered only by negative charges or electrons, it is possible to add an additional N+ active region 123 in the PMOS transistor without adding the P+ active region 124 in the NMOS transistor.

In another aspect, it is possible to additionally arrange an n-well region 199 between the PMOS transistor and the NMOS transistor, and parallel to the N+ guard ring 131, and the n-well region 199 is physically separated from the N+ guard ring 131 of the PMOS transistor. The occurrence condition of the latch-up is also increased by this way.

As mentioned above, when the latch-up of a logic circuit occurs, the chip is not able to work normally and the system needs to be reset. Accordingly, the present disclosure further provides a digital circuit (e.g., FIGS. 1-2 ) with an increased holding voltage to prevent the occurrence of latch-up without altering the routing of digital circuit or changing the circuit structure such that it is easily to be implemented in the standard logic cell.

Although the disclosure has been explained in relation to its preferred embodiment, it is not used to limit the disclosure. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the disclosure as hereinafter claimed. 

What is claimed is:
 1. A logic circuit, comprising: an n-well region; a PMOS transistor, arranged in the n-well region; an N+ active region, arranged in the n-well region adjacent to a source of the PMOS transistor; an N+ guard ring, arranged in the n-well region and physically separated from the N+ active region; a p-well region; an NMOS transistor, arranged in the p-well region; a P+ active region, arranged in the p-well region adjacent to a source of the NMOS transistor; and an additional n-well region, arranged between the PMOS transistor and the NMOS transistor, and physically separated from the N+ guard ring.
 2. The logic circuit as claimed in claim 1, wherein the additional n-well region is parallel to the N+ guard ring.
 3. The logic circuit as claimed in claim 1, wherein the PMOS transistor and the NMOS transistor respectively comprise a poly-Si gate connected by a poly routing.
 4. The logic circuit as claimed in claim 1, wherein the N+ active region is arranged at a side of the PMOS transistor close to the NMOS transistor, and the P+ active region is arranged at a side of the NMOS transistor close to the PMOS transistor.
 5. The logic circuit as claimed in claim 1, further comprising: a first contact of the N+ active region; and a third contact of the N+ guard ring, wherein the first contact and the third contact are both connected to a voltage source.
 6. The logic circuit as claimed in claim 5, wherein the N+ guard ring is not extended between the PMOS transistor and the NMOS transistor.
 7. The logic circuit as claimed in claim 1, further comprising: a P+ guard ring, arranged in the p-well region and physically separated from the P+ active region.
 8. The logic circuit as claimed in claim 7, further comprising: a second contact of the P+ active region; and a fourth contact of the P+ guard ring, wherein the second contact and the fourth contact are both connected to a ground voltage.
 9. The logic circuit as claimed in claim 7, wherein the P+ guard ring is not extended between the PMOS transistor and the NMOS transistor.
 10. A logic circuit, comprising: a PMOS transistor and an NMOS transistor, wherein a gate of the PMOS transistor is electrically connected to a gate of the NMOS transistor via a poly routing extending along a first direction, a first contact of the PMOS transistor covers on a P+ active region, which is configured as a source of the PMOS transistor, and an additional N+ active region adjacent to each other in the first direction in an n-well region, and a second contact of the NMOS transistor covers on an N+ active region, which is configured as a source of the NMOS transistor, and an additional P+ active region adjacent to each other in the first direction in a p-well region, a third contact, covering on an N+ guard ring, which is physically separated from the additional N+ active region, in the n-well region; and an additional n-well region, arranged between the PMOS transistor and the NMOS transistor, and physically separated from the N+ guard ring.
 11. The logic circuit as claimed in claim 10, further comprising: a fourth contact, covering on a P+ guard ring in the p-well region, wherein the fourth contact and the second contact are physically separated on a surface of the NMOS transistor, and the P+ guard ring is physically separated from the additional P+ active region.
 12. The logic circuit as claimed in claim 11, wherein the third contact and the first contact are configured to connect to a voltage source, and the fourth contact and the second contact are configured to connect to a ground voltage.
 13. The logic circuit as claimed in claim 10, wherein the additional n-well region is parallel to the N+ guard ring.
 14. The logic circuit as claimed in claim 10, wherein the N+ guard ring is not extended between the PMOS transistor and the NMOS transistor.
 15. The logic circuit as claimed in claim 10, wherein a first sub-contact is respectively arranged on the P+ active region and the additional N+ active region on the PMOS transistor, and the first sub-contacts are connected by a metal line to form the first contact, and a second sub-contact is respectively arranged on the N+ active region and the additional P+ active region on the NMOS transistor, and the second sub-contacts are connected by another metal line to form the second contact.
 16. The logic circuit as claimed in claim 10, wherein the additional N+ active region is not configured as a guard ring, and the additional P+ active region is not configured as a guard ring.
 17. The logic circuit as claimed in claim 10, wherein the third contact and the first contact are physically separated on a surface of the PMOS transistor.
 18. A logic circuit, comprising: an n-well region; a PMOS transistor, arranged in the n-well region; an N+ active region, arranged in the n-well region adjacent to a source of the PMOS transistor; a p-well region; an NMOS transistor, arranged in the p-well region and adjacent to the PMOS transistor in a first direction; a P+ active region, arranged in the p-well region adjacent to a source of the NMOS transistor; and an additional n-well region, arranged between the PMOS transistor and the NMOS transistor, wherein the N+ active region and the P+ active region are opposite to each other in the first direction across the additional n-well region. 